At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an exceptionally talented IP timing lead. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day.
This role is for a IP timing Engineer who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of pre-silicon development from definition to high quality tape-out.
Description
Development, ownership of IP level timing constraints both for regular and custom requirements from synthesis to sign-off to achieve sign-off quality timing convergence. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical Design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Minimum Qualifications
- At least 2+ years of experience in writing ASIC timing constraints and timing closure
Key Qualifications
Preferred Qualifications
- 5+ years of work experience
- knowledge of the ASIC design timing closure flow and methodology
- Expertise in STA tools (Primetime) and flow
- Knowledge of timing corners/modes
- Process variations and signal integrity related issues
- Hands on experience in timing/SDC constraints generation and management, proficient in scripting languages (Tcl and Perl) Familiarity with synthesis, DFT and backend related methodology and tools
- Strong communication skills and you will interface with a lot of different groups