RFIC - PLL Design Engineer
Do you have a passion for invention and self-challenge? Do you thrive with pushing the limits of what’s considered feasible. As part of an outstanding team, you’ll craft sophisticated, groundbreaking projects that deliver more performance in our products than ever before. You’ll work across fields to transform improved hardware elements into a single, coordinated design. Join us, and you’ll help us innovate new technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what wireless systems can do and improve the product experience for our customers worldwide.
The wireless RFIC team architects, designs, and validates radio transceivers integrated into sophisticated wireless SoCs. Our wireless organization is responsible for all aspects of wireless silicon development that transform the user experience at the product level, all of which is driven by an outstanding vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering. As an RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple’s groundbreaking wireless connectivity solutions into hundreds of millions of products!
As an RFIC-PLL Designer, you will provide analog and digital PLL solutions for wireless SoC and drive them to mass production for Apple. Responsibilities include:
- Lead design of radio transceiver chains including analog PLLs - VCOs, digital PLLs - DCOs, LOGen, and chain of blocks in RX, and TX for wireless connectivity products.
- Drive radio KPI (power, area, performance) to meet product requirements - Work with multi-functional teams, including platform architecture, wireless design, RF HW, and SW, to define radio features enabling wireless innovation.
- Work closely with RF Systems on block-level and high-level specifications of the PLL-LOGen, TX and RX line-ups and the accurate distribution of spec margins in the chain.
- Design of RF and Analog loopbacks for calibration and compensation.
- Work through Co-Existence scenarios and design to meet the CoEx requirements.
- Lead all aspects of the floorplan layout and verification of the design to ensure a successful tape-out.
- Provide design versus silicon measurements correlation and compliance with volume production specifications.
- BS and 10 + years of relevant industry experience.
- Solid experience with RF/analog and mixed-signal design experience in groundbreaking RF CMOS design.
- Experienced in the design and development of fractional N Synthesizers, Digital PLLs, Analog PLLs, and LO-Gen for high-performance applications and also low power applications.
- Hands-on experience in designing TDC, GRO, Digital Filters, Sigma Delta Modulators, Pre-scalers, and MMD, DCOs, PFD-CP, and VCOs. Modeling, analysis, and design of SD noise cancellation and spur cancellation techniques.
- Experienced in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS), and similar tools.
- Familiarity with mixed-signal mode verification methodology (SystemVerilog, AMS, Nanotime).
- Extensive experience in fractional N synthesizer and LOGen silicon characterization and debugging.
- Direct experience in designing and bringing wireless transceivers into mass production in deep sub-micron RFCMOS technology.
- Deep understanding of analog, mixed-signal, and RF circuit design. This includes LNAs, PAs, mixers, baseband filters, VGAs, and calibration methods associated with high-performance wireless systems.
- Familiarity with various RF transceiver architectures and their trade-offs, system specifications, and ability to work with system architects to translate system requirements into circuit requirements at the IC level.
- Proven capability working with digital design group for an optimum partition between digital and analog domain, and timing requirements.
- MSEE and/or PhD with extensive experience.
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