Mixed-Signal Verification Engineer
Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
In this role, you will be verifying RF/Mixed-Signal blocks and SOCs using SystemVerilog to create testbenches, checkers, models and tests. You will build and execute test plans to meet project schedule and metric requirements, including coverage metrics. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during aggressive schedules, we encourage you to apply.
In this role, core responsibilities include, but are not limited to the following:
• Review specifications and collaborate with the Design Team to extract features, define and execute verification plan.
• Develop top/block level Mixed Signal and Digital testbench and generate directed/ constrained random tests in a UVM framework.
• Build and reuse real numbered analog behavioral models of the Analog and Mixed Signal Circuits
• Build and reuse monitors, and checkers for RF, Mixed-Signal and Digital blocks.
• Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage.
• Write scripts for automation of flow.
• Improve Mixed Signal verification methodology.
- BS degree is required.
- Experience in UVM methodology and HDL (System Verilog, Verilog) for verification.
- Solid experience in Mixed Signal Verification or Real Numbered Modeling of Mixed Signal Systems.
- Modeling experience with RF/Mixed-Signal blocks and SOCs.
- Expertise building Mixed-Signal testbenches, checkers and tests using System Verilog.
- Strong verification skills in problem solving, constrained random testing, and debugging.
- Understanding of common analog/RF blocks and circuits.
- Experience with signal processing using Python or Matlab.
- Experience with Virtuoso Composer, ADE and HED.
- Experience with Software Engineering and Python.
- Ability to work well in a team and be productive under aggressive schedules to meet shared objectives and derive results.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.