GNSS Design Verification Engineer
Would you like to join Apple’s growing wireless silicon development team? Global Navigation Satellite Systems (GNSS) space vehicles transmit the power of a lightbulb, they are 13000 miles away, and are moving four kilometers per second. The received signals are commonly one hundred times weaker than cosmic microwave background radiation left over from the Big Bang and arrive next to interfering signals ten billion times stronger, just few MHz away. Our GNSS team is part of Apple's wireless SOC team. We are a vertically integrated engineering team spanning RF, mixed signal analog design, systems engineering, Design Verification, RTL design, firmware and software engineering, Test, and Validation. Our focus is on highly energy efficient and robust GNSS receiver design. We develop GNSS technology that touches hundreds of millions of lives, something we are passionate about.
As a GNSS Design Verification Engineer, you will be responsible for pre-silicon RTL verification of our GNSS IP and SoC subsystem. As part of our DV team, you will develop reusable testbench and verification environment deploying the latest methodology, working closely with GNSS and SoC front-end designers and Systems Engineers.
Build block/subsystem/chip level testbench using outstanding DV methodologies.
Build verification plan from specification and review with designers and systems engineers.
Architect testbench with maximum reusability in mind and build UVM libraries.
Generate directed and constrained random tests, debug failures, manage bug tracking, and close coverage. Create and analyze block/subsystem level coverage model and add test cases to increase coverage.
Low power verification and formal verification.
Improve DV flow and methodologies.
- BS with a minimum of 3 years of relevant experience.
- Experience with Wireless/DSP block/System-on-Chip verification.
- Advanced knowledge of SystemVerilog and in-depth understanding in UVM methodology.
- Solid verification skills in problem-solving, constrained random testing, and debugging.
- MSEE or beyond is preferred.
- Knowledge of SOC subsystem and low power verification experience.
- Experience with SystemVerilog Assertion (SVA).
- Knowledge of scripting (like Shell, Python, and Perl).
- Experience in mixed-signal modeling and simulation
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