CAD Chip Level Engineer -Physical Design

Haifa, Israel
Hardware

Summary

Posted:
Role Number:200279499
Will you help us design future generations of revolutionary Apple products? Are you an engineer with a strong foundation and real passion for building new technologies? Imagine what you could do here. At Apple, new ideas have a way of becoming outstanding products, services, and customer experiences very quickly. Every single day, people do amazing things at Apple. Do you want to impact billions of users by developing extraordinary products with a prime focus on accuracy and performance of the product? As a member of the PD top level CAD team, you will develop and support the top-level place and route methodology and flow. This flow is used by multiple projects at multiple sites. Strong knowledge of top level place and route flow, UPF, algorithm, scripting (TCL/Perl) and Makefiles are a must.You will interface with physical design teams, CAD team, and EDA vendors. Good communication/interpersonal skills are important

Key Qualifications

  • Candidate typically will have 5 years experience in hierarchical ASIC P&R and flow development
  • Experience with all aspects of ASIC PD including floorplanning, power-distribution, multi-voltage design, pad ring construction, placement, CTS, and routing
  • Understand hierarchical P&R issues including top-level floorplanning, pin-assignment, clock-distribution, critical-signal handling, UPF, MVRC, hierarchical abstractions (black-box, ILM, etc.), and dealing with pad-ring logic/IP
  • Strong TCL/Perl/Makefile scripting knowledge. Candidate should have experience developing complex algorithms, managing, and regressing P&R flows
  • Candidate should be familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies
  • Encounter knowledge is a plus

Description

Provide innovative solutions to improve quality of physical design Work with chip design teams to implement and customize design flows that are optimal for a given chip Provide documentation, training and new-user-support Responsible for diagnosis, resolution, regression of reported problems for multiple projects/sites Work with CAD team to integrate the flow into the larger infrastructure

Education & Experience

BSc/ MSc in Electrical Engineering or Computer Science.

Additional Requirements