Top-Level Physical Design Engineer

Haifa, Israel
Hardware

Summary

Posted:
Role Number:200279503
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented Physical Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. In this role, you will take part in the large scale SoC physical design cycle from netlist to tape-out, including full flow of back-end implementation and verification always meeting schedule and design goals.

Key Qualifications

  • You will have at least 5+ years of Physical Design experience of large scale SoC.
  • Deep knowledge about industry standards and practices in Physical Design, including Floor- planning, Place & Route and High Speed Interface Design
  • Proven experience in STA methodology and tools
  • Deep Understanding of all aspects of Physical construction and Integration
  • Proven experience in advanced nodes, including experience in technology migration
  • Proven understanding of scripting languages such as Perl/Tcl
  • Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level

Description

As a TopLevel Physical Design engineer you will be involved with all phases of physical design of high performance and low power SoC design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Full-chip Floorplanning based on close collaboration with architecture and design teams. Develop and validate high performance low power clock network guidelines. Perform top-level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical design verification flow at chip level and provide guidelines to fix LVS/DRC violations to other designers. Design and Implementation of High Speed interfaces at chip level, including routing, timing and power consumption aspects. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration.

Education & Experience

B.Sc. / M.Sc. Electrical Engineering / Computer Engineering

Additional Requirements

  • BSc/MSc/PhD in EE/CE
  • Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics. If you’d like more information about your EEO rights as an applicant, please click here. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. For more information, please click here.
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  • Apple's committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Learn more.