Standard Cell Design Methodology & Flow Engineer

Beaverton, Oregon, United States


Role Number:200424891
Do you love building without precedent? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking! Join us in an exciting silicon design group that is responsible for designing innovative ASICs, and you’ll help design the tools that allow us to bring customers experiences they’ve never-before envisioned. We have an extraordinary opportunity for Standard Cell Design Methodology and Flow Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with the custom digital circuits team and library development, making a critical impact in delivering products to market quickly.

Key Qualifications

  • We are looking for applicants with one or more of the following:
  • 5+ years in Library Characterization, Timing/Power/CCS Noise/Variation Modeling, Liberty Formats, Spice simulation, Static Timing and Power Analysis flows, etc.
  • Experience with timing modeling of large custom macros and complex sequential flops.
  • Experience with RTL development for digital components, the ability to run through synthesis with timing constraints and to perform block/full chip STA constraints and Timing analysis.
  • Exposure to Design For Test, scan concept and write DFT friendly RTL.
  • Understands all aspects of implementation specification, design, timing, power, and flow automation.
  • Data analysis and ML knowledge to study data trend and perform QA on big dataset with automation.
  • Flow automation skills in standard cells development and integration to improve execution efficiency. Experience of using TCL/Perl/Python.
  • Knowledge of FE modeling/Verilog and/or VHDL, and experience with various EDA tools for synthesis, place-route, Verilog simulation, spice simulation, formal verification, DRC/LVS, RC extraction and/or library characterization.
  • Proven understanding of device physics and process.
  • Familiar with foundry ecosystem and benchmarking practice.
  • Great interpersonal skills to champion initiatives internally and externally, and for effective communication with executive management and external partners.
  • Technical, analytical, and multi-functional collaboration skills.


Imagine yourself at the center of our ground breaking processor design in deep submicron technologies, and on standard cell library designs. You will drive concepts of transistor level circuit design, modeling, and performance analysis, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of talent engineers. As a Standard Cell Design Methodology and Flow Engineer for the custom circuits team, you will: - Be the interface to internal CAD team for planning production flows and with foundry on PDK requirements. - Collaborate with technology team on new process requirements and work with design/CAD team to enable relevant tools/flows. - Implement complex digital block in Verilog/SystemVerilog, run Synthesis with proper constraints and perform block/chip level STA and analyze the reports. - Be responsible for working with design/CAD team to formulate automation specifications of characterizing and modeling complex combo and sequential circuits. - Use data analysis techniques and/or advanced Machine Learning models to study the circuit trends in timing, power, and area, and to potentially detect quality issues in large datasets.

Education & Experience

BSEE/MSEE is required.

Additional Requirements