SoC Physical Design Engineer, Electrical Analysis



Weekly Hours: 42
Role Number:200486617
We are looking for talented engineers to join our Electrical Analysis team. In this role, you will be driving the electrical analysis and verification of an SoC. You will be working closely with multiple physical design teams and with other integration and analysis teams, like STA, power and package.


• As a member of our SoC physical design team, you will be performing various electrical analyses at the block or chip level, including : Gridcheck, Static/Dynamic IR, EM, Noise, Signal EM and ESD. • You will collaborate with the CAD/library/circuit technology/system teams for tech/flow evaluation, bring-up, validation and qualification for SoC chip development. • You will also work with the implementation team during the entire chip design cycle to drive EMIR test planning, analysis support, and sign-off closure for tape-out. • You will support cross-functional engineering efforts for the success of Apple’s SoC product development.

Minimum Qualifications

Key Qualifications

  • Solid background and knowledge of low-power circuit design, computer architecture, and digital systems.
  • Multi-year hands-on experience working on ASIC physical implementation and analysis flow for IP blocks as well as SoC fullchip.
  • Proficient in automating and debugging verification flows for digital VLSI design.
  • Knowledge with industrial EDA backend tools like Redhawk, PrimeRail, Voltus, or a similar tool is required. Experience with Innovus, Design Compiler, PrimeTime and Tempus is preferred.
  • Familiar with voltage drop budgeting, low-power design techniques, and sign-off criteria for solid-state digital circuit systems.
  • You have engaged in design tape-outs regarding power integrity signoff.
  • Circuit design background and SPICE experience are a plus.

Preferred Qualifications

Education & Experience

B.Sc / M.Sc Electric Engineering / Computer Engineering

Additional Requirements