CPU Physical Design and Integration Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Dynamic, thoughtful people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a processor design effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
- BS and 3+ years of relevant industry experience
- Experience with physical design, integration, and verification (PDV) experience on large processor and/or SoC designs
- Knowledge of industrial standards and practices in physical design, including floorplanning, partitioning, budgeting, place and route and physical verification
- Will be responsible for CPU floorplan, area optimizations, block partitioning and pin placements.
- Experience using synthesis & place-route tools
- Knowledge of low power design, physical construction, integration, PDV, DRC/LVS verification.
- Solid understanding of scripting languages, such as Perl/Tcl
- Solid understanding of CMOS circuit design. Layout design background is a plus
- Working knowledge of extraction, STA , EMIR methodology, and tools
- Ability to work well in a team, being an excellent problem solver, and self-motivated
As a CPU Physical Design and Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. - Full chip floorplan, area optimizations, block partitioning and pin placements - Own chip level place and route (PnR), final CPU layout database construction and verification (PDV) - Develop and validate Power Grid, including routability analysis - Drive custom layout integration - Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout - Work with SOC team to meet IP technical and delivery requirements - Participate in establishing CAD and physical design methodologies - Participate in flow development for chip integration and analysis - Scripting to automate tasks and improve debug efficiency
Education & Experience
BS and 3+ years of relevant industry experience