GPU FE Design Integration Engineer
Santa Clara Valley (Cupertino), California, United States
Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU! You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. This high visibility role in GPU FE Design Integration team includes close interaction with multiple teams, coordinating deliveries across projects and implementing/tracking quality controls while promoting efficiency.
- We are looking for someone to join our team who have:
- Proficiency in logic design principles, Verilog/System Verilog and scripting languages (Perl/Ruby/Python).
- Experience with scalable designs, design reuse, DFT insertion, LEC, Lint, codeline management, simulation and debugging tools.
- Knowledge of Power Intent (UPF/CPF), CDC, RDC, synthesis, physical design and STA.
- Familiarity with GPU/CPU Architecture and micro-architecture.
- Ability to analyze architectural and micro architectural details to drive design partitioning.
- Ability to close performance, power, area, functionality and lint for designs.
- Ability to solve complex problems across multiple technical domains.
- Ability to work well in a team and be productive under aggressive schedules.
The successful candidate will: - Own RTL integration, assembly, partitioning, transformation and analysis. - Package, qualify and deliver FE design collateral. - Triage logic equivalence failures between designs. - Ensure implementation readiness with RTL lint, clock/reset/power domain crossing checks and unit level synthesis. - Develop innovative methods to improve front-end design integration process. - Author specifications for design units. - Review and signoff specifications for customers and IP providers. - Collaborate effectively with Architecture, IP, DV, SOC, DFT, Synthesis, P&R and STA teams spanning multiple sites.
Education & Experience
We are looking for candidates with a minimum of BS + 10 years of experience.