GPU Top RTL Design Engineer

Austin, Texas, United States


Role Number:200460622
Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC)! You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices! At Apple, we push our designs to the limit to make amazing products. We want to delight our customers with hardware that performs great while delivering long battery life. As part of the mobile GPU design team, you will collaborate with Platform Architecture, Software, Design Verification, and Physical Design teams to deliver RTL and specifications for GPU power management, SOC interface logic, and shared IP. In addition, you will be responsible for integrating applicable IP from other teams to enable complete security, debug, and power management solutions.

Key Qualifications

  • Proven expertise in energy-efficient/low-power logic design.
  • Expertise in logic optimization, synthesis, timing analysis, floor-planning, power intent descriptions, and clock domain clock crossings.
  • Proficient in Verilog and/or System Verilog and scripting languages.
  • Solid experience with logic simulation and debug.
  • Ability to work well in a team and be productive under aggressive schedules.
  • 3+ years of industry experience.
  • Graphics hardware background a plus.


• Deliver high quality design collateral, including RTL, to Physical Design teams. • Create micro architecture specifications. • Specify clock, power, and interface descriptions to ensure optimized design. • Assess and integrate IP from other Apple teams. • Close timing, power, area, and lint for design by optimizing RTL and constraints. • Drive performance, power, area, and functional goals. • Provide schedules to IP teams and management. • Lead project milestones for on time delivery. • Collaborate effectively with IP teams spanning multiple sites.

Education & Experience

We are looking for candidates with a minimum of BS + 3 years of relevant experience.

Additional Requirements