Synthesis CAD Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200470916
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices!

Key Qualifications

  • Proficiency with TCL, Python or Perl scripting languages
  • Good knowledge of Logic design fundamentals through coursework or work experience
  • Familiarity with Verilog and SystemVerilog is a plus
  • Ability to write synthesizable RTL code is a plus
  • Knowledge or experience with industry standard synthesis tools is a plus
  • Exposure to static timing analysis tools is a plus


You will apply your hand-on skills in developing, improving and supporting the implementation flow from RTL through GDS signoff. You will be directly responsible to improve physical synthesis techniques through innovative scripts, flows and automation. Primary Responsibilities Will Include: - Develop and improve existing flows for Physical Synthesis and DFT Implementation - Support multiple design teams and work with cross functional teams to solve key physical synthesis challenges - Collaborate with other flows like Logic Equivalence, Static Timing Analysis and Low Power (UPF) Implementation - Work with tool vendors to resolve tool/flow issues

Education & Experience

Minimum requirement of Bachelors Degree + 0 years of relevant industry experience

Additional Requirements

Pay & Benefits