CPU Cache RTL Architect
Santa Clara Valley (Cupertino), California, United States
Hardware
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Apple’s Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products! We are looking for an experienced engineer that can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.
Key Qualifications
- Minimum BS and 3+ years of relevant industry experience
- CPU RTL and architecture experience, or Doctorate degree with CPU design/architecture as research focus.
- Knowledge and experience with the following as it relates to CPU cache design:
- Coherence protocols and interconnects
- High performance (low latency, high bandwidth) design techniques
- Memory subsystem queuing, scheduling; starvation and deadlock avoidance
- SRAM design basics
- Multiple clock/power domains and power management strategies
- Prefetchers, replacement policies
- Debug capabilities
- DFT strategies
- Error detection and correction
- Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools. Experience in C or C++ programming and interpretive languages such as Perl or Python.
- Knowledge of logic design principles along with timing and power implications and understanding of low power microarchitecture techniques.
Description
As a cache subsystem architect, you will own or participate in the following:
• Microarchitecture development and specification. From early high-level architectural exploration, through microarchitectural research and arriving at a detailed specification.
• RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.
• Performance exploration. Explore high performance strategies and work with the verification team to validate that the RTL design meets targeted performance.
• Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power.
Education & Experience
Minimum BS and 3+ years of relevant industry experience