Digital Mixed Signal Verification Engineer
Tokyo, Tokyo-to, Japan
Imagine what you could do here at Apple? Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. As a member of DMS(Digital Mixed-Signal) verification team in Technical Development Center in Tokyo, you will take on diverse challenges in verifying digital/mixed-signal designs. In this highly visible role, you will be at the center of chip design effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly. You will become part of a hands-on development team that fosters engineering excellence, creativity and innovation. Collaboration across teams is a key component of success at Apple. The right candidate will thrive in that type of environment. It's one of the most exciting aspects of the job. Dynamic, smart people and inspiring, innovative technologies are the norm here.
- We typically require at least 5 years of experience and we are looking for individuals with validated experience taking chips to production.
- Expertise creating and using real-numbered analog behavioral models in SystemVerilog.
- Familiarity with SystemVerilog, SV2012 Real, UDN/UDT, Wreal, Verilog-AMS.
- Experience at writing SystemVerilog Assertion.
- Able to understand analog schematics and analyze verification results.
- Experience at writing scripts in languages such as Perl or Python.
- Understanding of basic analog/mixed-signal blocks like Serdes, PLL, ADC, DAC.
- Experience with Virtuoso Composer, ADE, Analog simulators and Digital simulators.
- Nice to have knowledge of the mechanism of Mixed-Signal simulator and Interface Element.
- Business-level at English communication both in oral and written.
- Team spirit, excellent communication skills and the desire to take on diverse challenges.
As a MS Verification Engineer, you will be responsible for performing the verification on digital/mixed signal designs including: - Develop accurate and efficient analog behavior models in Verilog or System Verilog for analog blocks such as oscillator, ADC, DAC. - Help in developing core analog models like VCO, LPFs, etc - Verify analog functions for block-level and chip-level: for example, coding test scenarios and environments for analog verification and/or assertion. - Document verification results for formal review with Analog Designers. - Support the building the chip level DMS verification environment with DV engineer. - Support DV team for running chip-level mixed-signal co-simulation using Verilog models of analog IP. - Work with Analog Designers for setting up and running AMS simulation. - Enhance analog behavior model development methodology for better accuracy, improved simulation run time, quicker turn-around time.
Education & Experience
MSEE with 5 years of analog verification experience or analog design experience with behavioral modeling