DMS Modeling and Verification Engineer
Tokyo, Tokyo-to, Japan
Imagine what you could do here at Apple? Together we could help craft the next generation of the world’s finest devices! New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish! As a member of DMS(Digital Mixed-Signal) verification team in IC Design Center in Tokyo, you will tackle diverse challenges in verifying digital/mixed-signal designs. In this highly visible role, we will be at the center of chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly. You will become part of a hands-on development team that champions engineering excellence, creativity and innovation. Collaboration across teams is a key component of success at Apple. The right candidate will thrive in that type of environment. It's one of the most exciting aspects of the job. Dynamic, intelligent people and inspiring, innovative technologies are the norm here.
- 5+ years of experience in developing and verifying real-numbered analog behavioral models in Systemverilog.
- Solid understanding of Systemverilog, RNM, UDN/UDT/UDR, wreal, Verilog-AMS.
- Experience in Systemverilog testbench development.
- Understanding of analog/mixed-signal blocks like Filter, opAmp, ADC, DAC, VCO, A/DPLL, Serdes, etc.
- Working experience in Cadence Virtuoso Schematic Composer and ADE.
- Very good understanding of analog, and design background (to analyze verification results) is a strong plus.
- Experience in writing scripts in languages such as Perl or Python.
- Business-level at English communication in both speaking and writing.
- Team spirit, excellent communication skills and the desire to take on diverse challenges.
As a DMS modeling and verification Engineer, you will be responsible for modeling and verifying analog/mixed-signal designs including: - Develop accurate and simulation-efficient analog behavior models for analog/RF hard-IPs in Systemverilog. - Verify those analog behavior models are accurate representations of analog schematics. - Verify analog hard-IPs functionalities against its design specifications using those analog behavior models: for example, coding test scenarios and environments for analog verification and/or assertion. - Plan and execute modeling and functional verification, and document results for formal verification review. - Enhance analog behavior model development methodologies for better accuracy, improved simulation run time, quicker turn-around time.
Education & Experience
BSEE is required, MSEE/PhD in electrical engineering is a plus.