Senior Design Verification Engineer (Japan Design Center)
Tokyo, Tokyo-to, Japan
Why Apple? We live in a mobile and device driven world where knowledge of the physical world around us is needed! We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. Apple is meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that commitment. The success we are striving will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problems in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk! As a member of design verification team, you will have the responsibility for construction of verification environments, coding of test scenarios and assertions. In this capacity, your role will involve close collaboration with analog and digital design engineers.
- Typically requires a minimum of 10 years of experience in SystemVerilog or the other verification language.
- Hands-on experience of constrained random verification environments.
- Hands-on experience of Assertion Based Verification.
- Basic design background in support of verification results analysis.
- Knowledge with Object Oriented Programming.
• Construction of verification environment by using Verilog, SystemVerilog or UVM • Designing test plan for verification • Coding test scenarios, assertion and debugging for Digital Design
Education & Experience
- Knowledge of any one of verification language (UVM, OVM, or VMM)
- Familiarity with system design using C(C++) or Verilog
- Hands-on experience with formal verification (assertion-driven verification)
- ATE functional test pattern generation for logic testers