DMS Modeling and Verification Engineer (Japan Design Center)

Tokyo, Tokyo-to, Japan


Role Number:200323748
Imagine what you could do here at Apple! Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. As a member of DMS(Digital Mixed-Signal) verification team in IC Design Center in Tokyo, you will take on diverse challenges in verifying digital/mixed-signal designs. In this highly visible role, you will be at the center of chip design effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly. You will become part of a hands-on development team that fosters engineering excellence, creativity and innovation. Collaboration across teams is a key component of success at Apple. It's one of the most exciting aspects of the job!

Key Qualifications

  • 5+ years of experience in developing and verifying real-numbered analog behavioral models in SystemVerilog.
  • Solid understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS.
  • Experience in SystemVerilog testbench development.
  • Understanding of analog/mixed-signal blocks like Filter, opAmp, ADC, DAC, VCO, A/DPLL, Serdes, etc.
  • Working experience in Cadence Virtuoso Schematic Composer and ADE.
  • Solid understanding of analog circuit fundamentals.
  • Experience in writing scripts in languages such as Perl or Python.
  • Business-level English communication in both speaking and writing.
  • Team spirit, excellent communication skills and desire to take on diverse challenges.


As a DMS modeling and verification Engineer, you will be responsible for modeling and verifying analog/mixed-signal designs including: - Develop accurate and simulation-efficient analog behavior models for analog/RF blocks in SystemVerilog. - Verify analog behavior models are accurate representations of analog schematics. - Verify analog block functionalities against its design specifications using analog behavior models: for example, coding testbenches, test scenarios and assertions for analog functional verification. - Document modeling and verification results for formal review. - Enhance analog behavior modeling methodologies for better accuracy, improved simulation run time and quicker verification turn-around time.

Education & Experience

BSEE is required while MSEE/PhD in electrical engineering is a plus.

Additional Requirements

  • Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.