AIML -Hardware Engineer, Neural Acceleration

Seattle, Washington, United States
Machine Learning and AI


Weekly Hours: 40
Role Number:200441688
The Machine Intelligence, Neural Design (MIND) team employs HW/SW co-design to achieve best-in-class performance and energy efficiency for numerous use cases that deploy neural networks. We seek a Hardware Engineer to help define and implement features that would be realized in next-gen neural accelerators. Our team is comprised of HW, SW, and ML engineers working together in the area of Efficient ML. Our charter is to push the frontiers of perf and power for DNNs with minimal memory footprint. As a HWE, you will be responsible for designing low-power hardware accelerators for AI applications. This includes but is not limited to: architecting energy-efficient hardware designs, implementing changes in an in-house simulator, and/or implementing new features in an in-house compiler. Our ideal team member is courageous when it comes to trying new things, is adept at reasoning about systems performance, and is willing to iterate on ideas. We value team members with strong communication skills with experience working cross-functionally with HW, SW, and ML teams.

Key Qualifications

  • 2+ years of experience working on designing low-power hardware
  • Proficient in Python, working knowledge of C++


As a member of this team, you will use your background to: * Work with ML experts to co-design hardware solutions that further improve perf and power of neural workloads * Implement features in our simulation engine and compiler for next-gen accelerators * Benchmark and diagnose performance bottlenecks of deep learning models * Work with a variety of partners from all parts of the stack — from Apps to Compilation, HW Arch, and Silicon Validation

Education & Experience

Bachelor's, Masters or PhD degree in Electrical Engineering, Computer Science, or a related field

Additional Requirements

  • Preferred Qualifications:
  • * Deep understanding of computer systems and the interactions between HW and SW
  • * Strong communicator with ability to analyze complex and ambiguous problems
  • * Experience with backend compilation, HW/SW co-design, and/or performance optimization
  • * Familiarity with at least one deep learning framework (e.g., PyTorch, Keras, TensorFlow)
  • * Familiarity with ML model compression techniques (e.g., quantization, pruning) and their mapping to microarchitecture
  • * Debugging model conversion from a high-level framework to a target device for correctness and performance issues

Pay & Benefits