CPU Gate Level Synthesis/Verification Engineer
Santa Clara, California, United States
Hardware
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Apple’s Silicon Engineering Group (SEG) is looking for a hardworking engineer for CPU gate level verification. In this role, the candidate would be part of Apple’s industry-leading CPU design team, working in a multi-functional role to design verification flows and ensure that our CPUs meet the highest standards for functional verification.
Description
You will own the gate level verification of Apple’s high-performance CPU projects. Responsibilities include but are not limited to:
• Running top level formal verification, structural gate checks, low power checks, and gate level simulations
• Supporting design team in block level verification runs and debug
• Running synthesis on the RTL to find potential gate-level issues early, and providing feedback to the appropriate teams
• Creating scripts to automate synthesis and verification runs, and track the results of our various verification checks
• Working with the CAD team to further develop and enhance our verification flows
Minimum Qualifications
- Minimum BS and 10+ years of relevant industry experience
- Experience in digital logic design
- Experience with formal verification or simulation tools
- Experience with a scripting language
Key Qualifications
Preferred Qualifications
- The ideal candidate should possess CPU implementation and verification experience
- Knowledge of RTL-to-gate formal verification tools (LEC) and debug techniques, low power structural verification tools (VCLP), and gate simulation and X-propagation debug (Xcelium)
- Working knowledge of synthesis tools and flows and Perl and TCL scripting
Education & Experience
Additional Requirements
Pay & Benefits
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