Verification Student, SoC Group - Jerusalem Site
Jerusalem, Jerusalem District, Israel
Hardware
In this visible role, you will be responsible for taking part in a SoC verification process of a large-scale SoC. You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors. Apply sophisticated techniques to achieve verification with the highest quality, efficiency, and time-to-market. You will work closely with the design team to ensure timely delivery of quality designs. Working with methods to accelerate verification time. Involvement in Post Silicon Validation.
Key Qualifications
- - Experience in SoC verification is an advantage
- - Familiarity with verification environments, UVM, and SystemVerilog – an advantage
- - Knowledge of formal, hardware acceleration – an advantage
- - Scripting and programming experience using several of the following: Perl, e, Verilog, SystemVerilog, C, C++, and TCL
Description
Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave
The world is better than we found it. Join us to help deliver the next groundbreaking Apple products.
In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are encouraged to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop a verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage. Develop verification plans for all features under your care. Implement verification plans, including design bring-up, Design Verification environment bring-up, regression enabling for all features under your care, and de-bug the test failures. Develop block, IP, and SoC level test benches Track and report Design Verification progress using a variety of metrics, including bugs and coverage. Develop mixed-signal simulation environment, and work closely with analog team to ensure overall bug-free mixed-signal design.
Education & Experience
- Student of Computer science and Electrical engineering with 4 semesters till graduation