Wireless Design Verification Team Leader

Herzliya, Tel Aviv District, Israel
Hardware

Summary

Posted:
Role Number:200536667
Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team. As a Wireless Design Verification Team Leader, you will be responsible for pre-silicon RTL verification of communication subsystem including MAC, PHY, and interfaces. With deep understanding of communication systems and protocols, you will interact with DV methodologists, designers and communication systems engineers to develop reusable testbenches and verification environment deploying the latest methodology with metric driven verification.

Description

Do you have what it takes? Any successful manager on our team will have two foundational attributes: Excellent engineering skills; Management and leadership capabilities. This means you have deep experience in all aspects of verification, and you love being in the details and getting your hands dirty whenever possible. You will have a strong, dynamic personality that enables your leadership abilities and allows you to focus and direct a strong technical team. - You will rely on your multiple years of relevant experience in design verification and leading DV engineering teams to be successful in this role - We face daily challenges and will be looking for your previous successes in owning DV for complex designs - To drive verification plans we are consistently working with all teams involved in the process, including SoC, System architects, and Design teams - It's also important to us to work with our internal CAD team to help define flow improvements to allow you to be more productive and achieve higher quality - Drive state-of-art verification methodology and process

Minimum Qualifications

Key Qualifications

  • Management experience
  • 7+ years verification experience
  • Solid verification skills in problem solving, constrained random testing, and debugging
  • Advanced knowledge of SystemVerilog and DV methodology
  • Experience with MAC or PHY Verification - a plus
  • Self-motivated and dedicated with proven creative thinking capabilities
  • Leadership and excellent verbal and written communication skills
  • Ability to handle multiple tasks and prioritise work to meet deadlines

Preferred Qualifications

Education & Experience

BSc or MSc in Electrical Engineering or Computer Engineering

Additional Requirements