Cellular ASIC Design Integration Engineer
Irvine, California, United States
Hardware
Do you love crafting elegant solutions to highly sophisticated challenges? Do you intrinsically see the importance of every detail? As a member of our dynamic Cellular group, you'll be at the heart of chip design! You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions.
This high-visibility and critical role provides excellent exposure to multiple VLSI design technologies and flows. It also requires close working relationships with many functional teams!
Key Qualifications
- This position requires thorough knowledge of the ASIC design flow, FE and design verification, synthesis, scripting, and netlist generation.
- Knowledge of ASIC/SoC design flow.
- Knowledge of FE tools (CDC, RDC, LINT, Formal, LP Checks, LEC, PTPX) and Synthesis and STA flows.
- Strong knowledge of RTL design and HDL languages (Verilog, System Verilog, etc.)
- Strong analytical skills to be able to make design tradeoffs for best performance, low area, and low power.
- Experience in driving power improvements based on power analysis tools/flows.
- UPF flow for defining the power intent of chips with multiple power domains.
- Experience in writing efficient design synthesis and STA constraints.
- Work with the DV team to come up with a thorough verification plan and drive coverage closure.
- Design interfacing with PD for floor planning and timing closure.
- Experience with version control tools and handoff of design releases.
- Strong scripting skills to automate tasks and build scalable design flows.
- Self-starter, highly motivated, highly organized, and schedule-driven, which is a must.
- Familiarity with DFT, MBIST, and backend-related methodologies and tools is a plus.
Description
On our team you will have following responsibilities:
- Contribute to definition, architecture, design and development of cellular sub system.
- Perform all aspects of front end design flow including integration, connectivity, releases, design checks, verification reviews, mbist, dft, synthesis, timing constraints.
- Perform power analysis and analysis different design tradeoffs and drive power improvements.
- Develop design methodologies for scalable designs.
- Pre/Post silicon debug support.
Education & Experience
BS and 10+ years of relevant industry experience.