AMS Layout Designer
Imagine what you could do here at Apple? Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish!
We searching for a self-motivated engineer for the role of AMS Layout Designer. You will engage with forefront technology nodes to build outstanding custom analog designs used to connect our extraordinary products to the world as well as optimizing their performance. You will join a development team that values engineering excellence, creativity and innovation. You will become a valuable member of Apple's Japan Design Centre.
Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you help us design next revolutionary Apple products?
You will be responsible to deliver fully-verified, clean layout, this includes the following:
- Designing sophisticated layout for mixed signal, and analog circuits in deep sub-micron CMOS technologies.
- Reviewing and analyzing floorplans and complex circuits with circuit designers.
- Running complete set of design verification tools available on AMS blocks.
- Working with circuit design team to plan/schedule work and negotiate any necessary layout tradeoffs as needed.
- Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.
- Exceeding engineering specifications and expectations by working closely with the design team.
- Applying advanced CAD tools and mask design knowledge to deliver accurate and robust layout that meet stringent matching performance, area and power
- Typically requires more than 5 years of experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits
- Experience implementing analog layouts to achieve tight matching, low noise, and low power consumption. Layouts may include analog blocks, resistors, capacitors, pad IOs, ESD structures, etc.
- High level of proficiency in custom and standard cell based floor-planning and hierarchical layout assembly.
- Must understand techniques for handling IR drop, RC delay, electro-migration, self heating and coupling capacitance.
- Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard processes, and proactively work with circuit designer to identify the best approach to solving problems.
- High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
- Knowledge of MENTOR GRAPHICS or CADENCE layout tools.
- Excellent interpersonal skills and able to work with multi-functional teams.
- English communication with e-mail is required
- Scripting skills in PERL or SKILL are a plus, but not required
- Verbal communication in English is considered a plus
- Bachelors of Science, preferred in Electrical Engineering